FIG. 1 diagrammatically illustrates the integrated circuit layout of a conventional power (MOSFET) circuit, having a cascode (series) arrangement of a pair of MOSFET devices M1 and M2, which are capable of extremely fast switching times. A schematic equivalent of the dual MOSFET circuit layout of FIG. 1 is shown in FIG. 2. In such a layout, the physical geometries of terminal connection leads to the source and drain (or collector and emitter equivalents of the schematic of FIG. 2), shown at E2, C1 and C2E1, are relatively long, widely spaced, and extend at right angles to the semiconductor surface area where the internal component regions of the MOSFETs are disposed. As a consequence, such a terminal connection geometry inherently possesses substantial inductance, both mutual and self, which causes unwanted coupling, feedback and noise sensitivity among the source, drain and gate leads.
More particularly, in order to take advantage of the power MOSFET switching speed of such a device, gate charge must be supplied at a high rate. With the use of a voltage source as a common gate drive expedient, an inductive back voltage is induced in the gate lead, which slows switching speed. Another problem is the tendency of parallel arranged MOSFETs to oscillate, particularly if the gate drive conductors are arranged such that they encircle or surround the high current source/drain leads, causing positive feedback coupling.